1. Field of the Invention
The present invention relates to wafer-scale integrated circuits where there are a plurality of selectably interconnectable cells on the surface of a semiconductor substrate together with one or more ports and, starting at a port, the cells are testable and connectable in an overall working structure whose configuration is in part dependent on which of the cells pass the test.
2. The Prior Art
It is known to operate an integrated circuit and controller combination to connect cells in a simple, one-dimensional, unbranching chain across the face of an integrated circuit. The controller sends instructions to the terminal cell in the chain for connection to be made to a selectable neighboring cell. The controller then tests the newly-connected neighboring cell. If the test is passed the connection is confirmed and the last tested cell becomes the new terminal cell of the chain, ready to connect to another cell to test it. If the test is not passed, the original terminal cell is instructed by the controller to connect to an alternative, as yet untested neighboring cell. This is continued until a working neighbor is found. If no working neighbor is found, the controller severs connection to the terminal cell and examines the as yet untested neighbors of the previous terminal cell. This process of shedding the terminal cell and effectively shrinking the chain is continued until a terminal cell is found which has a previously-untested working neighbor which passes the test. The new-found working neighbor then becomes the new terminal cell and chain-growth is continued. Chain growth is stopped by the controller when either all accessible cells on the integrated circuit have been incorporated in the chain or when the chain has grown to include at least a predetermined number of cells.
The simple chain growth described has the disadvantage of rendering an unacceptably large number of cells non-incorporable into the chain. Every time the controller retreats down the chain by shedding terminal cells a cul-de-sac of cells which are known to be working is left behind. In a poly cellular wafer-scale integrated circuit having seventy percent of its cell capable of passing the functional test and where the thirty percent of non-functional cells are randomly distributed over the surface of the integrated circuit, as many as fifty percent of those cells capable of passing the test can be lost to the chain.
It is also known to operate an integrated circuit and controller combination to connect cells in a complex labyrinth across the surface of the integrated circuit. Each of the cells is in receipt of global commands from the controller. The cells are so configured that each can be connected to from any neighbor and can establish connection to any neighbor which has not already established connection to it. The global signals from the controller are used to cause inter-state stepping in a state machine in each cell. The state machine controls the flow of data in each cell and monitors the progress of the functional test either its own cell or a neighboring cell might be undergoing. The state machine then elects whether the functional test has been passed or not and whether or not inter-cell couplings are to be confirmed. The controller supplies instructions and data for the functional testing. The state machine operates in a first mode when it is first interrogated from a neighboring cell. It sets its cell into a sequence of operations which allow the cell to be the subject of the functional test. If its cell passes the test, the state machine confirms its new-found first connection. If its cell does not pass the test, the state machine shuts down the cell. Having passed the test, a subject cell becomes a tester cell, its state machine selecting a neighboring cell which has not yet had connection established thereto to turn that neighboring cell into a subject cell. At the end of the labyrinth growth, when either all accessible cells have been incorporated into the labyrinth, or when the labyrinth comprises at least a predetermined number of cells, the state machines are collectively placed in a state wherein the integrated circuit becomes a functional data processing element.
The labyrinth of connected cells is extremely efficient in picking up cells, capable of passing the functional test, for incorporation. Its growth is also quite rapid compared to the growth of a chain, since in the chain growth can occur from only one point at a time, while in the labyrinth growth occurs from all tester cells simultaneously.
The labyrinth-connectable integrated circuit has the considerable disadvantage of having, in each cell, a very high proportion of circuit elements concerned only with the state machine and with the monitoring of the functional test. The data processing capacity of each cell is thereby drastically reduced, since there is an optimum area size for each cell beyond which the proportion of functional cells becomes unacceptably low.
There are situations where, despite its efficiency, the labyrinth is incapable of incorporating a very high proportion of potentially usable cells. Since the cell connecting strategy is contained within the state machine in each cell, it is out of the control of the external controller, which can therefore do nothing to modify connections. The exact topology of the labyrinth is also undiscoverable to the controller. The controller cannot therefore take note of a successful growth pattern and reimpose it at a later time without the time wasting delay of reperforming the growth routine. The individual cells are autonomous in their interconnections, and cannot be instructed by the controller, even if it could discover the topology of the labyrinth, to selectably change or establish any inter-cell connection without the strategy and actual performance of the limited repertoire of the state machine.
It is therefore desirable to provide a combination comprising a polycellular integrated circuit and a controller wherein the controller is capable of knowing the topology of the tested and interconnected structure of cells, where the controller can select the inter-cell connections of each cell according to a controller-contained strategy allowing the incorporation of a high proportion of potentially usable cells, where the controller is provided with a simple method and apparatus for controlling that strategy, and where an already-discovered interconnection pattern can be re-imposed on an integrated circuit without the necessity for wasting time repeating the test-and-select routine which originally established the pattern of connection.